Computing machines and devices carry out instructions to provide functionality. An instruction may include a memory access command that prompts a processor of the computing device to access an electronic storage. The electronic storage may be organized into an address space including unique memory locations that are each accessible with a different memory address. In response to the memory access command, the processor may access the electronic storage at one or more of the different memory addresses.
A memory address may be encoded using a binary number that is expressed with a number of bits. For example, the memory address may be encoded using 8-bits, 16-bits, 32-bits, and/or with another number of bits.
Instructions may be characterized by a code size. The number of bits that encode the memory address to be accessed may affect the code size of a memory access command. The address space may include a region (e.g., a high bank and/or a low bank) in which the memory addresses are encoded using a relatively greater number of bits (e.g., high bank addresses) and/or a relatively fewer number of bits (e.g., low bank addresses). For example, memory access commands to access a high bank address may have a greater code size than memory access command to access a low bank address.
Since instructions are stored and processed, as code size increases, so may a demand on storage and/or energy resources of the computing machine or device. For example the memory access command to access the high bank address may result in consumption of more storage and/or energy resources than would a memory access command to access the low bank address.